A user may configure a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) to perform a desired function and thus avoid having to design an application specific integrated circuit (ASIC) to perform the same task. Because designs and system requirements may change and evolve, users of programmable logic devices can simply reprogram these devices without having to engineer another ASIC. Although programmable logic devices thus offer users significant advantages, a concern may be raised concerning their reliability. Specifically, the configuration of programmable logic devices often depends upon a volatile configuration memory such as SRAM that may become corrupted. Should a configuration bit in the configuration memory change its value, a programmable logic device may cease to perform the function desired by a user. In critical applications, such a failure could be disastrous.
Volatile configuration memory may become corrupted in a number of ways. For example, all materials, including the semiconductor substrate used to form a configuration memory, are naturally radioactive. Although this natural level of radioactivity is quite low, it still involves the emission of alpha particles. These high-energy particles may then interact with a memory cell and corrupt its value. Alternatively, power brownout, i.e., a glitch or drop in supply voltages over a certain duration, may corrupt the programmed value of the memory cells. Cosmic rays also generate charged particles that may corrupt the programmed values. Because all these sources of memory error do not relate to internal hardware flaws in the memory cells but rather to external effects that cause errors, they may be denoted as sources of soft error.
In the current state of the art, a programmable logic device user may verify configuration memory contents during the configuration process. For modern programmable logic devices, the configuration RAM can be quite large. To retrieve the contents of such a large memory, which may be several million bits or larger, and directly compare the retrieved bits to what was originally written would be quite complex. Thus, compression schemes such as cyclic redundancy check (CRC) have been employed to represent the combined state of the configuration RAM using a relatively small signature. Retrieving the signature and comparing the retrieved signature to that for the originally written bits is thus a less onerous task than a direct comparison. In a conventional programmable logic device, however, a user then has no way to re-verify the configuration memory contents during subsequent operation of the programmable logic device (i.e., while the device is operable to accept input data and generate output data). This inability to detect soft error during operation exists despite the aggravation of soft error probability as programmable logic device geometries continue to shrink.
Accordingly, there is a need in the art for programmable logic devices configured to allow the verification of the configuration memory during programmable logic device operation.